1. Field of the Invention
The present invention relates to a semiconductor large scale integration (LSI) device including a scan test circuit.
2. Description of the Background Art
In a large scale integration device having complicated functions, a scan test is routinely used as an on-production test. In the scan test, as described in Japanese patent laid-open publication No. 2002-296323, a route, termed a scan path, is provided in advance between flip flops disposed on the input and output ports of plural combinatorial circuits, or circuit blocks, constituting a large scale integration device, these flip flops being concatenated together into a string when testing.
More specifically, test data are serially shifted through the flip flops on the scan path to be supplied in parallel in the form of input data to the circuit blocks. Data resultant from the testing and developed in parallel from the circuit blocks are temporarily held in the flip flops, and thereafter read out in series over the scan path. It is determined whether or not expected values corresponding to the test data have been obtained, thus verifying the functions of the circuit blocks. In such a scan test, it is necessary to use, at the outset, information on the circuit configuration, such as net list, in connection with the circuit blocks to prepare test data for a variety of functional tests and expected values thereof.
When a licensee manufactures a large scale integration device having a specific circuit block built therein under the license granted from a licensor, information on the circuit configuration for the specified circuit block may often not be available to the licensee. There may also be occasions where it is not desirable that the rate of detecting malfunction on a specific circuit block is affected by the configuration of another circuit interconnected thereto. In such cases, a scan separator circuit is often used for conducting a test with the scan path isolated.
Conventionally, a large scale integration device includes two circuit blocks, for example. The circuit blocks, i.e. the first and second blocks in the direction of flowing data signals, are interconnected with a plurality of scan separators, which are further interconnected in serial to each other to form a cascade of stages.
When test data are supplied to the second circuit block, one selector included in the scan separators is switched to form a scan path from the test input terminal of the first cascade stage through all of the scan separators to the test output terminal of the final cascade stage. Then, a corresponding plurality of bits of test data are sequentially received in series on the test input terminal in synchronism with clock signals supplied to the plurality of the scan separators. This causes the bits of test data to be retained in the respective scan separators. The other selector of the scan separators is in turn switched to output the bits of test data in parallel to the second circuit block.
When reading out data resultant from the processing by the first circuit block, the first selector of the scan separators is switched to receive a corresponding plurality of signals from the first circuit block to latch them. When the scan separators are supplied with one pulse of the clock signals, they latch the signals thus received.
The selectors of the scan separators are then switched to form the scan path from the test input terminal through the scan separators to the test output terminal. When the scan separators receive the clock signals, they sequentially shift the data thus latched along the scan path through the cascaded stages in synchronism with the clock signals to serially output the bits of test data from the test output terminal.
With the above-described large scale integration device, it was necessary to provide a corresponding plurality of scan separators to the number of the signals transferred from the first circuit block to the second circuit block of interest, thus increasing the scale of the entire circuit. The scan separators are used only for on-manufacture testing, and not at all when operating in the ordinary use of the integrated circuit although it is desirable to minimize the circuit scale required.
It is an object of the present invention to make the scan separator more intensive to suppress the circuit scale of the large scale integration device from increasing.
A semiconductor integrated circuit according to the present invention comprises a first circuit block, a second circuit block and a plurality of scan separators transferring in ordinary operation, signals between the first and second circuit blocks, and isolating, in testing operation, the first and second circuit blocks from each other. Each of the scan separators is provided for every two signals transferred from the first circuit block to the second circuit block.
More specifically, the scan separator includes a first selector for selecting one of two signals, output from the first circuit block, in response to an input selector signal, a second selector for selecting scan data afforded from outside or from one of the scan separators in one of the cascaded stages which precedes when receiving a scan control signal, the second selector being adapted for selecting an output signal of the first selector when not receiving the scan control signal, a flip flop for holding an output signal of the second selector to output the output signal in the form of scan data to outside or to one of the scan separators which follows in the cascaded stages, and for sending the output signal to the first selector as the input selector signal in response to a clock signal, and a third selector for selecting the two signals or the output signal of the flip flop in response to an output selector signal, and for affording a selected signal to the second circuit block.
Further according to the present invention, each of the scan separators is provided for two signals. Hence, the scan separator may be made more intensive than a conventional large scale integration device where each scan separator is provided for one signal, with the result that the circuit scale of the entire large scale integration device may be suppressed from increasing.
Alternatively, each of the scan separators is provided for four of the signals transferred from the first circuit block to the second circuit block. Each of the scan separators includes a first selector for selecting one of the four signals output from the first circuit block in accordance with a combination of a first input selector signal and a second input selector signal. The first input selector signal is scan data supplied from outside or from one of the scan separators in one of the cascaded stages which precedes. Each of the scan separators further includes a second selector for selecting scan data supplied from outside or from one of the scan separators in the cascaded stages which precedes when receiving a scan control signal, and for selecting an output signal of the first selector when not receiving the scan control signal. Each scan separator also includes a flip flop for holding an output signal of the second selector to output the output signal in the form of scan data to outside or to one of the scan separators which follows in the cascaded stages, and for sending the output signal to the first selector as the second input selector signal in response to a clock signal, and a third selector for selecting the four signals or the output signal of the flip flop in response to an output selector signal, and for affording a selected signal to the second circuit block.